1. Field of the Invention
The present invention relates to an amplifier circuit in a CMOS integrated circuit and, more particularly, to a differential amplifier circuit.
2. Description of the Related Art
Presently, in a CMOS integrated circuit, alternating signals are normally amplified using a CMOS inverter. For example, in a quartz oscillation circuit as shown in FIG. 1, an oscillation output of a CMOS inverter X1 at a first stage accompanied by a quartz oscillator Xxe2x80x2t connected across input and output terminals thereof is sent to subsequent stages after being amplified further by a CMOS inverter X2 as a buffer circuit.
The potential of an operating point of the oscillation output of such a CMOS inverter fluctuates owing to process-related factors, fluctuation of power supply potential caused by the oscillation operation and the like to be out of a predetermined threshold of the CMOS inverter X2. It has been therefore difficult to set the duty ratio of the oscillation output at 1/2, and the duty ratio has been set in a certain allowable range.
A limitation is sometimes placed on the value of a current supplied to the CMOS inverter X1 in order to reduce power consumption. In such a case wherein the voltage amplitude of the oscillation output is reduced, the influence of the fluctuation of the operating point potential on the duty ratio becomes too significant to ignore.
Under such circumstances, according to the present invention, the first and second differential amplifier circuits amplify the first and second signals regardless of their operating point potentials with their duty ratios kept unchanged, and two outputs therefrom are combined into one output. This makes it possible to prevent the operating point potential of the output from varying due to process-related factors, fluctuation of the power supply potential caused by the oscillation operation and the like.
The first differential amplifier circuit used here comprises a differential input portion comprising the first and second MOS transistors and the first current mirror circuit comprising the third and fourth MOS transistors whose drains are connected to the drains of the first and second MOS transistors, respectively. The second differential amplifier circuit used here comprises a differential input portion comprising the fifth and sixth MOS transistors and second current mirror circuit comprising the seventh and eighth MOS transistors whose drains are connected to the drains of the fifth and sixth MOS transistors, respectively. There is provided an output buffer circuit for generating an output signal based on a signal generated at the drain of the fourth MOS transistor and a signal generated at the drain of the eighth MOS transistor.
Here, response of the differential amplifier circuit can be improved by especially connecting all of the gates of the MOS transistors forming the first and second current mirror circuits and connecting the drain of the fourth MOS transistor and the drain of the eighth MOS transistor to provide an input to a CMOS inverter as the output buffer described above. In addition, the reduction of power consumption can be further promoted by providing either or both of the first current control circuit for commonly connecting the sources of the first, second, seventh and eighth MOS transistors to the first potential source and controlling a current flowing therein and the second current control circuit for commonly connecting the sources of the third, fourth, fifth and sixth MOS transistors to the second potential source and controlling a current flowing therein.
Further, it is possible to suppress a current flowing through the output buffer and to promote the reduction of power consumption by providing the first current control circuit for commonly connecting the sources of the first and second MOS transistors to the first potential source and controlling a current flowing therein and the second current control circuit for commonly connecting the sources of the fifth and sixth MOS transistors to the second potential source and controlling a current flowing therein, and by using a circuit as the output buffer which comprises the ninth MOS transistor of the first conductivity type whose gate is connected to the gate of the fourth MOS transistor and a tenth MOS transistor of the second conductivity type whose gate is connected to the drain of the eighth MOS transistor with the drains of the ninth and tenth MOS transistors being connected to each other to generate an output signal at the connection point.
There is provided a differential amplifier circuit which includes the first differential amplifier circuit including a differential input portion comprising a pair of MOS transistors of the first conductivity type and the second differential amplifier circuit including a differential input portion comprising a pair of MOS transistors of the second conductivity type, in which the first signal and the second signal having a cycle corresponding with that of the first signal are input to both of the first and second differential amplifier circuits differential amplification output based on the first and second signals and in which the differential amplification outputs of the first and second amplifier circuits are combined to provide an output.
The differential amplifier circuit may comprise:
the first MOS transistor of the first conductivity type which receives the first signal at its gate;
the second MOS transistor of the second conductivity type which receives the second signal having a cycle corresponding with that of the first signal at its gate;
the first current mirror circuit comprising the third and fourth of MOS transistors of the second conductivity type, the drains of the third and fourth MOS transistor being connected to the drains of the first and second MOS transistors, respectively, the gates of the third and fourth MOS transistors being connected to each other and the gate and drain of the third MOS transistor being connected;
the fifth MOS transistor of the second conductivity type which receives the first signal at its gate:
the sixth MOS transistor of the second conductivity type which receives the second signal at its gate;
the second current mirror circuit comprising the seventh and eighth MOS transistors of the first conductivity type, the drains of the seventh and eight MOS transistors being connected to the drains of the fifth and sixth MOS transistors, respectively, the gates of the seventh and eighth MOS transistors being connected to each other and the gate and drain of the seventh MOS transistor being connected; and
an output buffer circuit for generating an output signal based on a signal generated at the drain of the fourth MOS transistor and a signal generated at the drain of the eighth MOS transistor.
Preferably, the gates of the third and fourth MOS transistors and the gates of the seventh and eighth MOS transistors are connected, and the output buffer circuit is a CMOS inverter whose input terminal is connected to the connection point between the drain of the fourth MOS transistor and the drain of the eighth MOS transistor.
Also preferably, the output buffer circuit includes the ninth MOS transistor of the second conductivity type whose gate is connected to the drain of the fourth MOS transistor and the tenth MOS transistor of the first conductivity type whose gate is connected to the drain of the eighth MOS transistor, and the drains of the ninth and tenth MOS transistors are connected to each other to generate an output signal at the connection point.
It is also preferable to provide either or both of the first current control circuit for commonly connecting the sources of the first, second, seventh and eighth MOS transistors to the first potential source and controlling a current flowing therein and the second current control circuit for commonly connecting the sources of the third, fourth, fifth and sixth MOS transistors to the second potential source and controlling a current flowing therein.